High-Speed LVDS (SERDES) Transceiver

SKU SKU65

$4000.00

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1 (this product is downloadable)

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General Description

High-speed LVDS (SERDES) transceiver with up to 8 serial data lanes, generic data width and integrated asynchronous FIFO. Ideal for standard LVDS links such as Channel link®, Camera link®, FPD link®, FlatLink® etc. Capable of data rates of up to 1 Gbps per lane on higher-end FPGAs and SoCs.

Key Design Features

- Separate Tx/Rx pair
- Up to 8 serial data lanes
- Parallel data widths up to 128-bits wide
- Parallel-to-serial mux ratio up to 16:1
- Fully configurable clocking architecture
- Data rates of up to 1 Gbps per lane
- Integrated asynchronous FIFOs
- Data underflow / overflow error detection
- Bitwise data alignment at receiver
- No receiver source clock required
- Robust and simple to implement using twisted pair cable
- Supports industry standards such as Camera link®, Channel link®, FPD link® etc.
- Compatibility and / or replacement for a wide range of commercial SERDES LVDS ICs
- Examples include: SN65LVDS*, SN75LVDS*, DS90CR*, DS90UR* and THC63LVD* series ICs

Applications

- High bandwidth SERDES interfaces for all FPGA, SoC and ASIC
- Implementation of 'virtual' ribbon cable
- Transport of high-bandwidth digital video
- Point-to-point comms over a few meters

View datasheet