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Floating-point Mathematics

IP Cores for high-speed pipelined floating-point arithmetic operations
High-speed fully pipelined 32-bit floating-point multiplier based on the IEEE 754 standard. Results have a latency of only 4 clock cycles. Ideal for floating-point pipelines, arithmetic units and processors.
$3000.00
High-speed fully pipelined 32-bit floating-point square-root function based on the IEEE 754 standard. Features a generic latency from 2 to 24 clock cycles. Ideal for floating-point pipelines, arithmetic units and processors.
$3000.00
High-speed fully pipelined 32-bit floating-point divider based on the IEEE 754 standard. Features a generic latency from 2 to 49 clock cycles. Ideal for floating-point pipelines, arithmetic units and processors.
$3000.00
High-speed fully pipelined 32-bit floating-point adder/subtractor based on the IEEE 754 standard. Results have a latency of 4 clock cycles. Ideal for floating-point pipelines, arithmetic units and processors.
$3000.00
Converts 32-bit floating-point numbers to fixed-point representation. The fixed-point output has a configurable word and fraction width. Floating-point inputs are based on the IEEE 754 standard. The design features a high-speed, fully pipelined architecture with a 2 clock-cycle latency.
$2000.00
Converts fixed-point numbers to 32-bit floating-point representation. The fixed-point input has a configurable word and fraction width. Floating-point outputs are based on the IEEE 754 standard. The design features a high-speed, fully pipelined architecture with a 2 clock-cycle latency.
$2000.00