Digital Signal Processing
IP Cores for DSP applications
FIR filter designed for very high sample rate applications up to 600 MHz. Organized as a systolic array, the filter is modular and scalable, permitting the user to specify large order filters without compromising maximum attainable clock-speed. Matlab®, FDAtool and Simulink® compatible.
FIR filter designed for high sample rate applications with symmetrical coefficients and an even or odd number of taps. Features configurable coefficients and data width. Design uses only half the number of multipliers compared to a normal FIR. Matlab®, FDAtool and Simulink® compatible.
2nd order IIR filter sometimes referred to as a 'bi-quad'. Internally, it has a fully pipelined architecture permitting the highest possible sample rates for IIR filtering. The SOS block is modular allowing any number of SOS blocks to be joined in series to implement higher order IIR filters.
Multi-channel FIR filter permits any number of inputs to be multiplexed into the same filter architecture. Much cheaper than using multiple FIR filter designs in parallel. Ideal for filtering dual-channel inputs such as complexed valued I/Q.
Fully configurable Nyquist decimation filter (down-sampler) with decimation factors from 2 to 2^N. The FIR filter is highly optimized for both speed and area and is ideal for a wide range of multi-rate DSP applications.
Digital Automatic Gain Control function (AGC). Chooses the best possible slice of a data sample to maximize the gain and dynamic range of the input into your DSP pipeline. Works with both signed and unsigned numbers. Programmable data width. Programmable AGC iteration period.