Floating-point to Fixed-point Converter

General Description

Converts 32-bit floating-point numbers to fixed-point representation. The fixed-point output has a configurable word and fraction width. Floating-point inputs are based on the IEEE 754 standard. The design features a high-speed, fully pipelined architecture with a 2 clock-cycle latency.

Key Design Features

- 32-bit floating-point input
- Signed fixed-point or integer output
- Configurable word width (up to 32-bits)
- Configurable fraction width (up to 23-bits)
- IEEE 754 compliant
- High-speed fully pipelined architecture
- Only 2 clock-cycles of latency
- FPGA clock rates of 300MHz+
- Low area footprint

Applications

- Floating-point pipelines and arithmetic units
- Floating-point processors
- Interfacing between float/fixed number systems

View datasheet

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