Master serial controller compatible with the popular Philips® I2C standard. Features a simple command interface and permits multiple I2C slaves to be controlled directly from your FPGA, CPLD or ASIC device. Exceeds the Philips high-speed spec. pushing data rates well above 4 Mbits/s.
Slave serial controller compatible with the popular Philips® I2C standard. Permits an I2C Master to communicate with your FPGA, CPLD or ASIC device via a set of user-defined config and status registers. Supports standard (100 kbits/s), fast (400 kbits/s) and custom rates in excess of 4 Mbits/s.
Master serial interface compatible with the popular SPI™ standard in both half-duplex and full-duplex modes. Features a simple command interface and permits multiple SPI slaves to be controlled directly from your FPGA, ASIC or SoC.
Slave serial interface compatible with the popular SPI™ standard. Permits an SPI Master to communicate with your FPGA, ASIC or SoC. The SPI Slave supports up to 512 custom registers that are accessible using a set of simple SPI read and write commands.
UART compatible Serial Interface Controller with receive and transmit FIFOs and support for all standard bit rates from 9600 to 921600 baud. UART is used extensively in test equipment and is the simplest way to to control your FPGA-based system using a micro-controller, PC or remote device.
Allows simple connectivity between a UART 2-wire port (Tx/Rx) and an I2C compatible bus. Allows simple programming and debug of an I2C device using a remote PC and terminal program.
High-speed LVDS interface solution for the Sony® FCB-EV range of HD1080p cameras. Offers simple implementation and connectivity for all Xilinx® FPGAs (other FPGAs and technologies supported on request). Typical cameras include the popular FCB-EV7520 and FCB-EV7320 COTs cameras for 1080p60 and 1...
High-speed LVDS (SERDES) transceiver with up to 8 serial data lanes, generic data width and integrated asynchronous FIFO. Ideal for standard LVDS links such as Channel-link®, Camera-link®, FPD-link®, FlatLink® etc. Capable of data rates of up to 1 Gbits/s per lane on higher-end FPGAs.
JEDEC® compliant FLASH memory controller ideal for interfacing to a wide range of parallel FLASH memory components such as the popular SST39 series from Microchip®. Features a fully synchronous command interface and a set of configurable timing parameters for compatibility with different devices.
Encoder/Decoder pair that implements the standard IBM® 8b/10b line code for a DC-balanced serial data stream. The 8b/10b code is a common encoding scheme used for the transmission of serial AC-coupled data with embedded clock over larger distances.