Floating-point Square-root

General Description

High-speed fully pipelined 32-bit floating-point square-root function based on the IEEE 754 standard. Features a generic latency from 2 to 24 clock cycles. Ideal for floating-point pipelines, arithmetic units and processors.

Key Design Features

- 32-bit floating-point arithmetic
- IEEE 754 compliant
- High-speed fully pipelined architecture
- Trade off latency vs. speed

Applications

- Floating-point pipelines and arithmetic units
- Floating-point processors

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