Fixed-point to Floating-point Converter

General Description

Converts fixed-point numbers to 32-bit floating-point representation. The fixed-point input has a configurable word and fraction width. Floating-point outputs are based on the IEEE 754 standard. The design features a high-speed, fully pipelined architecture with a 2 clock-cycle latency.

Key Design Features

- Signed fixed-point or integer input
- 32-bit floating-point output
- Configurable word width (up to 32-bits)
- Configurable fraction width (up to 23-bits)
- IEEE 754 compliant
- High-speed fully pipelined architecture
- Only 2 clock-cycles of latency
- FPGA clock rates of 300MHz+
- Low area footprint

Applications

- Floating-point pipelines and arithmetic units
- Floating-point processors
- Interfacing between float/fixed number systems

View datasheet

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