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Floating-point Adder

Floating-point Adder
SKU SKU13
$3000.00
Quantity
1 (this product is downloadable)

General Description

High-speed fully pipelined 32-bit floating-point adder/subtractor based on the IEEE 754 standard. Results have a latency of 4 clock cycles. Ideal for floating-point pipelines, arithmetic units and processors.

Key Design Features

- 32-bit floating-point arithmetic
- IEEE 754 compliant
- High-speed fully pipelined architecture
- Only 4 clock-cycles of latency
- FPGA clock rates of 300MHz+
- Low area footprint

Applications

- Floating-point pipelines and arithmetic units
- Floating-point processors

View datasheet

IEEE Floating-point Adder

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