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Asynchronous FIFO

Asynchronous FIFO
SKU SKU41
$1000.00
Quantity
1 (this product is downloadable)

General Description

Asynchronous FIFO optimized for very high-speed operation. Features a configurable data width and depth. The component uses Gray-coded read/write pointers for highest reliability when synchronizing between different clock domains. Ideal for asynchronous interfaces where speed it critical.

Key Design Features

- Dual-clock architecture
- Configurable data width
- Configurable depth of 8 or 16 entries
- Gray-coded read/write pointers
- FIFO Full and Empty flags
- Simple valid-ready pipeline interface protocol
- Compatible with AMBA® AXI4-stream, Altera® Avalon-ST and Xilinx® local-link
- 400 MHz+ operation on basic FPGA devices

Applications

- Synchronizing between clock domains
- Registering the datapath on and off chip
- General purpose buffering
- Adapting to different data rates

View datasheet

Asynchronous FIFO

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