AXI4-Stream Protocol Interface

General Description

This service is a design-specific modification to any of our existing IP Cores to support the AMBA® 4 AXI4-Stream Protocol. The AXI4-Stream protocol is an open specification originated by ARM and is popular among many FPGA and ASIC vendors - especially Xilinx® FPGAs and SoCs.

The AXI4-stream protocol shares a similar set of flow-control signals to our own valid-ready data streaming protocol. For this reason, it is very easy to adapt our IP-Cores to the AXI4 specification. In addition, we can also provide versions of our IP to support other streaming protocols such as Altera® Avalon-ST and legacy Xilinx® interfaces such as local-link.

(Please contact Zipcores to discuss your requirements in full before purchase)

Key Design Features

- Full AXI4-Stream compatibility
- Applicable to all our streaming IP-Cores
- Choice of byte, packet or frame-based transfers (where applicable)
- Support for other streaming interfaces such as Avalon-ST and local-link

Applications

- High data rate master-slave streaming interfaces
- Compatibility with a wide range of third-party designs and IP

View datasheet

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