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Pipeline Register

Pipeline Register
1 (this product is downloadable)

General Description

Self-flushing register element with a configurable data width. Data flows in and out of the register in accordance with a simple valid-ready pipeline interface protocol. The component is used as a fundamental building block in pipelined architectures.

Key Design Features

- Fully synchronous design
- Configurable data width
- Simple valid-ready streaming protocol
- Compatible with AMBA® AXI4-stream, Altera® Avalon-ST and Xilinx® local-link
- Self flushing architecture
- 1 cycle latency


- High-speed data streaming interfaces - e.g. DSP and video
- Interfacing between other pipeline elements
- Registering the datapath to improve timing
- Registering the datapath on and off chip
- Simple buffering

View datasheet

Pipeline register

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