1. IP Core as VHDL synthesizable source code

Our IP Cores are provided as clearly readable VHDL source code which is compatible with all well known synthesis tools including Xilinx® ISE, Altera® Quartus, Synplify® and Synopsys®.

2. VHDL test bench

Every IP Core is supplied with its own VHDL testbench which instantiates the Core in an example configuration. Each testbench is self-contained and generates input and output test vectors as a text file. All our testbenches have been proven using Modelsim®, the popular VHDL simulator supplied by Mentor Graphics.

3. Comprehensive PDF datasheet

All our cores are backed up with a fully comprehensive datasheet. The datasheet includes everything needed to take full advantage of ZIPcores IP. Topics covered in each datasheet include:

- Block diagrams
- Key design features
- Example applications
- Pin-out descriptions
- Functional specifications
- Functional descriptions
- Generic parameter descriptions
- Functional timing diagrams
- Performance data
- VHDL source file descriptions
- Functional testing and how to test your core
- Synthesis Results and strategy

4. Single-site IP Licensing Agreement

With every core sold, we include the ZIPcores IP License Agreement which outlines the legal aspects relating to the use of ZIPcores IP. Please take time to read the agreement thoroughly as the use of ZIPcores IP is strictly bound by the terms and conditions of this document.