CALL US: +34 667 249 415    ZIPcores - Digital Video Processing - Video Frame Buffer / Genlock Video Frame Buffer / Genlock   General Description Video Frame buffer permits an asynchronous video source to be buffered in an external memory. Features a generic 32-bit memory interface suitable for all memory types including SDRAM, DDR2, DDR3 etc. Ideal for adapting to different pixel rates and frame rates. Scalable architecture allows multiple video inputs to be genlocked together. Key Design Features - Asynchronous video input - Output video synchronized to the system clock - Simple user interface looks like a FIFO - Supports any video resolution above 2x2 pixels* - Supports 16, 24 or 32-bits per pixel   e.g. 4:2:2 YCbCr, 4:4:4 YCbCr, 24-bit RGB etc. - Supports frame skip and frame repeat - Programmable memory burst size - System diagnostics to monitor performance - Single 32-bit R/W port to external memory - Optimized for all synchronous memory types - Fully scalable for any number of video inputs - FPGA clock rates of 350MHz+ * External memory permitting By cascading a number of Video Frame buffer modules in parallel, multiple asynchronous video sources may be buffered and genlocked together. Low-cost Xilinx® Spartan-6 reference design available on request Applications - Buffering video frames in external memory - Real-time digital video applications - Genlocking of multiple video sources - Adapting to different pixel rates and frame rates - Essential component in video processing pipelines View full product datasheet: Details   SKU SKU55 Price: $3000.00 Options   Quantity 1 (this product is downloadable)   Also available in this category Digital Video Scaling Engine Bilinear Video Scaling Engine Text Overlay Module Digital Video Overlay Module 2D Graphics Overlay Module Video Frame Buffer / Genlock Variable-Tap Video Scaling Engine Video Timing Generator Video Test Pattern Generator Versatile Video Controller Multi-format Video Deinterlacer

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