At ZIPcores, we design and sell Intellectual Property (IP Cores) for implementation on Semiconductor Devices. We are a small team of experienced Engineers with a broad knowledge of Digital Hardware Design spanning various fields. We offer a wide range of IP Cores for a variety of applications from basic building blocks to more complex systems. Our cores are written in clear, readable VHDL and are synthesizable across multiple technologies - whether it be FPGA, CPLD or ASIC.

"Our aim is to provide quality, portable IP that is not tied
to any particular technology or vendor tool"

In addition, you will find that most of our cores are generic in nature. We think it is important to offer flexible IP that may be reconfigured and used in different applications.

"Design re-use is the key! Our generic designs mean that
ZIPcores IP can be reused time and time again"

Before being released for sale, our IP is subject to stringent testing and verification. Generally, we use Modelsim® to perform a VHDL simulation of the Hardware. In parallel, we also develop equivalent functional models in software. Typically, the models are written in PERL or C. We capture input and output vectors during the course of both hardware and software simulations and check their equivalence as part of the verification process.

"We take pride in ensuring our IP is verified and tested
to the highest standards"

All our cores are synthesized using the Xilinx® ISE and Altera® Quartus suite of design tools. The compatibility of our IP with both popular technologies is our upmost concern. After Place and Route, we analyze the results to ensure the design is optimal for it's intended purpose. As a general rule, our philosophy is to try and optimize our designs for clock-speed and pipeline latency at the expense of area. Of course, this philosophy may not always fit in with the requirements of the customer, and to this end, ZIPcores would be happy to rework a core for a specific design goal.

"Our design philosophy is to design cores optimized for
clock-speed and minimal pipeline latency"

Finally, depending on the complexity of the core, the design is tested on a real FPGA development board. Only when we are 100% satisfied that the design is functionally correct are we happy to release our IP for sale.

"You can rest assured that our IP will give you a reliable and optimum solution for your SoC design - every time"

Simon Doherty
Managing Director - www.zipcores.com