Synchronous FIFO with generic width and depth

General Description General purpose synchronous FIFO with configurable depth and data width. The component uses a simple valid/ready pipeline interface protocol and features full/empty flags and a FIFO fullness counter. The FIFO can be configured to use register or RAM-based storage. Key Design Features - Fully synchronous design - Configurable depth and data width - Register or RAM-based storage - Full/Empty flags and FIFO fullness counter - Simple valid/ready pipeline interface protocol - Output register option for improved timing - 1 cycle latency Applications - General purpose buffering and rate adaptation - Interfacing between other pipeline elements - Datapath timing improvements View full product datasheet: Details   SKU SKU4 Price: $500.00 Options   Quantity 1 (this product is downloadable)