Synchronous FIFO

Synchronous FIFO
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General Description

General purpose synchronous FIFO with configurable depth and data width. The component follows a simple valid-ready pipeline interface protocol and features full/empty flags and a FIFO fullness counter. The FIFO can be configured to use register or RAM-based storage.

Key Design Features

- Fully synchronous design
- Configurable depth and data width
- Register or RAM-based storage
- Full/Empty flags and FIFO fullness counter
- Simple valid-ready streaming protocol
- Compatible with AMBA® AXI4-stream, Altera® Avalon-ST and Xilinx® local-link
- 1 cycle latency


- General purpose buffering
- Adapting to different data rates
- Interfacing between other pipeline elements
- Datapath timing improvements

View datasheet

Synchronous FIFO

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