Synchronous FIFO

Synchronous FIFO
SKU SKU40
$1000.00
Quantity
1 (this product is downloadable)

General Description

General purpose synchronous FIFO with configurable depth and data width. The component follows a simple valid-ready pipeline interface protocol and features full/empty flags and a FIFO fullness counter. The FIFO can be configured to use register or RAM-based storage.

Key Design Features

- Fully synchronous design
- Configurable depth and data width
- Register or RAM-based storage
- Full/Empty flags and FIFO fullness counter
- Simple valid-ready streaming protocol
- Compatible with AMBA® AXI4-stream, Altera® Avalon-ST and Xilinx® local-link
- 1 cycle latency

Applications

- General purpose buffering
- Adapting to different data rates
- Interfacing between other pipeline elements
- Datapath timing improvements

View datasheet

Synchronous FIFO

: *
: *
: *
 
 
HD-Video Development Board
HD-Video Development Board
desc here
$3000.00
Ultra-speed FIR Filter
Ultra-speed FIR Filter
desc here
$2000.00
Arctan Function
Arctan Function
desc here
$2000.00
AXI4-Stream Protocol Interface
AXI4-Stream Protocol Interface
desc here
$1000.00
ADS-B 978 MHz (UAT) Receiver
ADS-B 978 MHz (UAT) Receiver
desc here
$0.00
Symmetrical FIR Filter
Symmetrical FIR Filter
desc here
$2000.00
IP Core upgrade package
IP Core upgrade package
desc here
$0.00
Cosine Function
Cosine Function
desc here
$2000.00
UART Serial Interface Controller
UART Serial Interface Controller
desc here
$2000.00