General Description
Slave serial interface compatible with the popular SPI standard. Permits an SPI Master to communicate with your FPGA, CPLD or ASIC device. The controller uses a series of registers as a data structure to communicate between Master and Slave.
Key Design Features
- SPI Compliant
- Simple SPI programming
- Configurable number of config registers
- Configurable number of status registers
- Configurable clock polarity (CPOL)
- Configurable clock phase (CPHA)
- FPGA comms up to 50 Mbits/s
Applications
- SPI slave communication via your FPGA/ASIC
- Inter-chip board-level communications
- Serial comms at higher data rates than other protocols such as I2C and USB1.0
View datasheet
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