ZIPcores IP Cores for FPGA, CPLD and ASIC ZIPcores IP Cores for FPGA, CPLD and ASIC
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ZIPcores IP Cores for FPGA, CPLD and ASIC
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 Peripheral and Communications Interfaces
ZIPcores - Peripheral and Communications Interfaces - SPI Master Serial Interface Controller

Printable version

SPI Master Serial Interface Controller

SPI Master Serial Interface Controller 

General Description

Master serial interface compatible with the popular SPIŽ standard. Features a simple command interface and permits multiple SPI slaves to be controlled directly from your FPGA, CPLD or ASIC device.

Key Design Features

- SPI Compliant
- Full-duplex or Half-duplex operation
- Simple command interface
- Input and output FIFOs
- Supports up the 16 slave devices
- Configurable clock polarity (CPOL)
- Configurable clock phase (CPHA)
- Configurable clock frequency
- FPGA comms between 10-20Mbits/s

SPI Master Serial Interface Controller

Applications

- Inter-chip board-level communications
- Driving SPI slave devices from your FPGA
- Serial comms at higher data rates than
  other protocols such as I2C and USB1.0

View full product datasheet: SPI Master Serial Interface Controller

Details
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SKU SKU32
Price: $1500.00

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