ZIPcores IP Cores for FPGA, CPLD and ASIC ZIPcores IP Cores for FPGA, CPLD and ASIC
ZIPcores IP Cores for FPGA, CPLD and ASIC   ZIPcores IP Cores for FPGA, CPLD and ASIC
ZIPcores IP Cores for FPGA, CPLD and ASIC
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ZIPcores IP Cores for FPGA, CPLD and ASIC
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 FIFOs, Datapath and Pipeline Elements
ZIPcores - FIFOs, Datapath and Pipeline Elements - Pipeline Register with generic width

Printable version

Pipeline Register with generic width

Pipeline Register with generic width 

General Description

Self-flushing register element with a configurable data width. Data flows in and out of the register in accordance with a simple valid/ready pipeline interface protocol. The component is used as a fundamental building block in pipelined architectures.

Key Design Features

- Fully synchronous design
- Configurable data width
- Simple valid/ready pipeline interface protocol
- Self flushing
- 1 cycle latency

Applications

- Interfacing between other pipeline elements
- Pipeline timing improvements
- Registering the datapath in and off chip
- Simple buffering

View full product datasheet: Pipeline register

Details
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SKU SKU2
Price: $150.00

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FIFOs, Datapath and Pipeline Elements Peripheral and Communications Interfaces Caches and Memory Management Fixed-point Mathematics IEEE Floating-point Mathematics Digital Signal Processing Digital Modulation Digital Video Processing
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