ZIPcores IP Cores for FPGA, CPLD and ASIC ZIPcores IP Cores for FPGA, CPLD and ASIC
ZIPcores IP Cores for FPGA, CPLD and ASIC   ZIPcores IP Cores for FPGA, CPLD and ASIC
ZIPcores IP Cores for FPGA, CPLD and ASIC
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Zipcores - News archive

Jan 10, 2012

Zipcores IP for Xilinx, Altera and Lattice FPGAs


As we enter 2012, Zipcores is proud to be celebrating it's 200th collaborative project based on FPGA technology.

FPGA news1

If you are developing a new and innovative electronic product, then FPGAs offer excellent flexibility and processing power.

FPGA news 2

Whether it be an initial prototype or commercial product, our Engineers can help you turn concept into reality.

FPGA news 3

Get a head-start and begin your design with one of our IP Cores from our extensive library.

All our Cores are technology independent and are suitable for both Xilinx®, Altera® and Lattice® FPGAs.

(Our IP can even be ported directly to ASIC if necessary)

Click here for support!
 

Oct 13, 2011

IP Cores for Xilinx 7-series FPGAs


Zipcores' video IP is perfectly placed to take advantage of the next-generation devices from Xilinx® such as the new Kintex-7 and Virtex-7 FPGAs.

Xilinx7 news 1

Clocking at over 300MHz on Kintex-7, our video IP is ideal for the latest HD technologies.

What's more, our designs support resolutions of 4K (or better) and frame rates in excess of 100Hz!

Xilinx7 news 2

Whether you're looking for high quality video scaling, on-screen displays, blended video overlays or special effects, our IP has a lot to offer.

Xilinx7 news 3

And of course, all our IP is 'soft' and 'future proof'. Our designs are shipped as portable VHDL source code, compatible with both FPGA and ASIC.

If you have a specific requirement then please contact one of our Engineers who would be happy to talk to you directly.

Click here for support!
 

Jun 27, 2011

Our latest VVC core

Our latest Versatile Video Controller (VVC) makes it even easier to synchronize and process multiple-video channels.

The VVC core is ideal for a wide range of video applications including: video scaling, multi-window displays, Picture-in- Picture (PiP) and alpha-blending operations.

VVC news 3

The standard VVC core supports 2 x 24-bit RGB video inputs, with the option to support 16 or more if necessary. Other colour formats and functionality may be added on request.


VVC news 4

Spartan 6


If you would like to evaluate any of our video IP we can provide a Xilinx® Spartan 6 reference design on request. Let us know if we can be of further help!

Click here to learn more!  

Mar 16, 2011

Make your old SDTV formats new again

Make your old SDTV formats new again with our wide range of high-quality video deinterlacing solutions.

Our algorithms deliver sharp progressive video without combing or tearing. The end result is an awesome display at near HD quality!

Deinterlacer news

Our deinteralcer IP cores are ideal for both FPGA and ASIC. They are simple to integrate and compatible with all current interlaced video formats such as 480i, 576i, 1080i etc.

Spartan 6


If you would like to evaluate any of our video deinterlacing solutions (or any of our video IP cores) we can provide a Xilinx® Spartan 6 reference design on request.

Please contact us for further details.

Click here to learn more!  

Jan 10, 2011

LVDS (SERDES) solutions for FPGA

The Zipcores LVDS Transceiver offers a high-bandwidth SERDES solution for all types of FPGA.

The IP Core is suitable for a wide range of Point-to-Point comms - from the serialization of control busses ('virtual' ribbon cable) to the transport of high quality digital video over a few meters.

LVDS SERDES news

The only requirement is that your FPGA has LVDS capable I/O buffers and a basic PLL or DCM in it's technology library. The rest is is plain sailing!

What's more, our LVDS solutions may be implemented using standard off-the-shelf CAT5E Ethernet cable.

LVDS SERDES news

The LVDS Transceiver is also fully configurable for compatibility with many other LVDS devices. By modifying the generic settings, it's easy to support protocols such as: Channel-link®, FPD-link® and FlatLink® via your FPGA!

Click here to learn more!  

Aug 4, 2010

Video deinterlacing made easy

Introducing our new high-quality Video Deinterlacer IP Core.

The core is compatible with all interlaced video formats and is capable of supporting resolutions up to 4096x4096 pixels.

Deinterlacer news

The deinterlacer is simple to integrate and supports three different deinterlacing algorithms: BOB, ELA and LCI.

Our proprietary version of LCI eliminates sawtooth, combing and motion-artifacts without softening. Ideal for converting 'legacy' SDTV formats to fully progressive HD.

Spartan 6


If you would like to evaluate our video deinterlacer IP Core (or any of our video products) we can provide a Xilinx® Spartan 6 reference design on request. Please contact us for further details.

Click here to learn more!  

May 24, 2010

Versatile Video Controller Core

Our Versatile Video Controller Core (VVC) is a high performance video processor with integrated dual frame buffer, high-quality video scaling and PiP support.

VVC core news 1

Implementing key video IP in one unique package, the VVC core is ideal for a wide range of multi-format displays including: PiP, dual-screen, scaled and blended video overlays.

VVC core news 2

What's more, the VVC core is easy to integrate into all FPGA technologies - clocking at 200MHz on even the most basic platforms.

Spartan 6

Also, why not request our new Xilinx® Spartan 6 VVC reference design and give a new lease of life to your video products!

Click here to learn more!  

Mar 8, 2010

Video Frame buffer for all memory types

We have released a new high speed generic Video Frame Buffer suitable for all common 16, 24 and 32-bit digital video formats.

With FPGA clock rates in excess of 350MHz, there's no need to worry about video bandwidth problems any more!

Video Frame Buffer

The VFB offers a generic 32-bit memory interface with programmable burst transfers optimized for all synchronous memory types - whether it be normal SDRAM or the latest DDR3 technology.

Spartan 6 comment

Also, why not request our new Xilinx® Spartan 6 VFB reference design. The design interfaces directly to the embedded Spartan 6 Memory Controller Block (MCB).

Designing memory interfaces has never been easier!

Click here to learn more!  

Jan 19, 2010

Introducing our variable-tap video scaler

Our new variable-tap video scaling engine offers a new degree of flexibility in digital video scaling. Using our proprietary algorithm, the scalers are simple to use and easy to implement.

Thumbnail images

The video scalers are capable of scaling video by any factor in x and y. They offer adjustable image quality and require only basic configuration - with no need for coefficient programming. What's more, they require no frame buffer and may be inserted in your video pipeline as you would a simple FIFO.

Variable-tap video scaler

The variable-tap scaler really comes into its own when scaling down by large factors - for instance, the generation of high-quality thumbnail images.

When downscaling by factors of two or more, our variable-tap scaling engine is the ideal choice.

Click here to learn more!  

Oct 16, 2009

ZIPcores Pixel Display Pipeline (PDP) solutions

ZIPcores offer a comprehensive range of of Video IP Cores for the display of 2D Graphics and Video content. Ideally suited for FPGA, our video cores are small, fast and compatible with all major FPGA vendors.

Pixel Display Pipeline

Our Video IP Cores share a common interface, allowing the architect to add, retro-fit and cascade modules seamlessly together. The result is a low-risk, high performance solution with short development cycles and low implementation costs.

See our PDP application note to learn more!  

Aug 14, 2009

Text and 2D-graphics Overlay modules

ZIPcores would like to introduce their new range of text and 2D graphic overlay cores. They offer a simple way to generate text and graphical displays without the need for complex programming.

Controlled via a simple read/write buffer, the cores are ideal for use with a simple uP or uC. They also come with the option of UART, SPI or I2C interfaces for extra flexibility.

Set top box

Text and 2D graphic video overlays are used extensively in today's digital video products. From consumer digital set-top boxes to automotive and industrial instrumentation - the list of applications is extensive.

Automotive dashboard

The cores are packed with features including 8-bit alpha-blending, fully anti-aliased 2D graphics, a programmable colour palette and a support for a wide range of animated effects.

Click on the Digital Video Processing section to learn more!  

Jun 8, 2009

Video Scalers prove popular with LCD display apps

ZIPcores are proud to announce the continued success of their range of Video Scaler products.

Since their release at the beginning of 2009 they have excelled in a number of LCD display applications - from panel mounted displays to ruggedized tablet PCs.


LCD display applications

Our scalers permit the conversion of source video into any aspect ratio or image resolution. They are small, easy to use and ideal for FPGA-based video solutions.


VGA to HD1080 Conversion


What's more, they offer high quality scaling at 24-bits per pixel - supporting resolutions from 16x16 to 4095x4095 pixels!

Scaling ratios may be fixed or dynamically changed on a frame-by-frame basis. Pixel filters are polyphase with 16-phases and fully programmable coefficients.

Click on the Digital Video Processing section to learn more!  

May 4, 2009

RF Power-Amplifer Precorrection

High-Power RF amplifiers are generally designed to provide maximum efficiency when driven at maximum output power. One downside is that the PA typically has a non-linear characteristic close to saturation.

For wideband signals such as WCDMA and OFDM, the result is the generation of unwanted Intermodulation products close to the central carrier.

Digital Precorrection

Zipcores has released a Digital Precorrection System that can correct the non-linear characteristic of the PA. The result is a much cleaner output signal with up to 20dBs recovered in the spectral shoulders!

The PA Precorrection system is available with a range of programming interfaces such as I2C, SPI and UART ... and once implemented on an FPGA, the circuit may be controlled easily via an external MCU.

Ideal for Digital TV broadcasting and Mobile base-station applications where optimum PA efficiency is essential.

Click on the Digital Modulation section to learn more!  

Mar 31, 2009

Serial interfaces that push the limits of performance

We've added a fresh perspective to some well established serial interfaces. Our I2C Master/Slave controller cores push the limits of I2C performance - exceeding the Philips® I2C High-speed spec. at 4Mbits/s!

I2C waveform

And why not take advantage of our new range of SPI® controllers. With data rates between 10 and 40Mbits/s, SPI offers much better data bandwidths than UART, I2C or USB 1.0.

SPI waveform

All our Controllers are easy to implement and offer complete flexibility with programmable clocking and generic design. What's more, I2C and SPI remain an industry standard and offer compatibility with literally thousands of of-the-shelf ICs.

Click on the Peripheral Interfaces section to learn more!  

Feb 5, 2009

Digital Video Scalers

We are excited to announce the release of three new Video Scaler Cores. The cores are available as independent Horizontal and Vertical scalers or as a complete Digital Scaling Engine.

VGA to HD1080 Conversion

All our scalers offer seamless scaling either up or down and feature a series of polyphase (16-phase) output filters for studio quality RGB-video output.

Ideal for conversion of video formats in any aspect ratio or resolution, they offer the ultimate flexibility for HDTV, home media and custom video applications.

What's more, the scalers are small, with minimal use of RAM resources and multipliers. Great for FPGA-based video solutions.

Click on the Digital Video Processing section to learn more!  

Jan 15, 2009

Our Christmas promotion is extended

Extended ZIPCORES Promotion!

Our Christmas promotion has been extended throughout the month of January. For any IP Core purchased up to the 31st January 2009, we are pleased to offer our customers 50% discount on a second IP Core*.

Remember that all our Cores are backed up by quality datasheets which are freely available from our site. What's more, once you buy, our Design Engineers are eager to help you integrate your IP as soon as possible - whether your chosen technology is FPGA, CPLD or ASIC.

We have worked in a wide range of application areas from DSP to Digital Comms to high-speed Pipelined Processors. If there's something you would like us to design for you then we're only an email away.

A Very Happy new year to all our Customers

* On receipt of payment of first IP Core we will send you a 50% discount coupon. (Discount applies to the the lower priced core). For more details, please complete our our web-based support form.  

Nov 27, 2008

Promotion

ZIPCORES Christmas Promotion!

For any IP Core purchased during the month of December 2008 or January 2009, we are pleased to offer our customers 50% discount on a second IP Core*.

Remember that all our Cores are backed up by quality datasheets which are freely available from our site. What's more, once you buy, our Design Engineers are eager to help you integrate your IP as soon as possible - whether your chosen technology is FPGA, CPLD or ASIC.

We have worked in a wide range of application areas from DSP to Digital Comms to high-speed Pipelined Processors. If there's something you would like us to design for you then we're only an email away.

A Very Merry Christmas to all our Customers

* On receipt of payment of first IP Core we will send you a 50% discount coupon. (Discount applies to the the lower priced core). For more details, please complete our our web-based support form.  

Nov 4, 2008

UART - The workhorse of the Instrumentation industry

ZIPcores have added a new UART controller core with FIFO buffering, flexible configuration, and a small area footprint. What's more, it supports data rates up to 921600 baud.

UART remains one of the surest and simplest ways of interfacing to your FPGA-based system from your PC COM ports.

UART was pioneered by the likes of IBM with it's convention of storing characters as 8-bit ASCII codes. The first commercial chips to support the protocol arrived in the 1970's and it's been around ever since.

UART is ideal for interfacing between microcontrollers, home computers, and remote devices.

To this day, UART remains the protocol of choice for many thousands of companies, and remains the workhorse of the test and instrumentation industry.  

Oct 22, 2008

FIR Filters with 500MHz+ sample rates

ZIPcores FIR Filter cores are fast, compact and easy to implement.

Based on a systolic array architecture, all our filters are modular and scalable, permitting the user to specify large order filters without compromising maximum attainable clock-speed.

What's more, our filters are fully generic with configurable coefficients, data width and number of taps.

Some of our filters are capable of sample rates of 500MHz+ on the latest Xilinx FPGAs!  

Oct 20, 2008

ZIPcores Development Centre now online!

ZIPcores is pleased to announce the opening of it's new online development centre. The site provides a library of FREE circuits coded in VHDL whose purpose is to help in the development and test of your FPGA and ASIC devices.

All the circuits are provided voluntarily by the ZIPcores team and we aim to add one or two circuits per month as the site develops.

Current circuits on offer include a 32-bit Linear Feedback Shift Register (LFSR) used to generate random sequences and, more recently, an FPGA-based 'Logic Analyser' which is being developed under the Opencores initiative.

For an up-to-date list of available circuits, please visit www.opencores.org for more information.  

Oct 10, 2008

Introducing our I2C controllers

Why not take advantage of our high-performance I2C interface products with controllers that exceed the Philips® I2C High-speed mode specification.

Both our I2C Master and Slave controllers push the limits of I2C performance, achieving data rates of up to 4Mbits/s on standard FPGA devices.*

Our Controllers offer ease of use and ultimate flexibility with programmable clocking and data set-up and hold times.

Not only that, I2C remains an industry standard and offers compatibility with literally thousands of chips - from DACs and LCD drivers to Video and RF ICs.

What a great way to communicate with 2 pins!

* Test scenario:
Xilinx Virtex-II FPGA target system, Default LVTTL (3.3V) x12 tristate drivers, SLOW slew rate, 4K7 external pull-ups, 6 Slave devices loading the bus.  

Sep 30, 2008

ZIPcores IP Cores for the latest Xilinx and Altera FPGAs

If you are in the Semiconductor business, ZIPcores can save you time, effort and money by providing off-the-shelf IP Cores for your SoC design!

Commerical FPGAs continue to take a quantum leap forward with Xilinx currently offering a 65nm process Virtex 5 FPGA and Altera with it's latest Stratix IV device boasting an incredible 45nm minimun feature size.

Remember that ZIPcores IP Cores are compatible with all popular technologies including these very latest Xilinx and Altera FPGAs.  

Sep 12, 2008

ZIPcores officially opens

Welcome to ZIPcores. At ZIPcores we offer a new and accessible approach to buy IP for FPGA, CPLD and ASIC platforms.

Our E-commerce site has a range of ready-to-use cores that are instantly available for download. Alternatively, if you have a specific IP Core that you would like designed or modified we offer a personalized design service. For more information, please fill in our web-based support form  

 

Bestsellers

1. Digital Video Scaling Engine
2. SPI Slave Serial Interface Controller
3. I2C Master Serial Interface Controller
4. Direct Digital Synthesizer
5. I2C Slave Serial Interface Controller
6. Pipelined Divider with generic width
7. Text Overlay Module
8. Video Timing Generator
9. Bilinear Video Scaling Engine
10. UART Serial Interface Controller
11. SPI Master Serial Interface Controller
12. Pipelined Square Root with generic width
13. 4-Quadrant Arctan Function
14. Generic Ultra-speed FIR Filter
15. 32-bit Floating-point Multiplier
16. Asynchronous FIFO with generic width
17. High-speed symmetrical FIR Filter (even taps)
18. Synchronous FIFO with generic width and depth
19. High-speed symmetrical FIR Filter (odd taps)
20. Pipelined Multiplier with generic width and depth
21. 2D Graphics Overlay Module
22. Digital Video Overlay Module
23. Video Test Pattern Generator
24. Versatile Video Controller
25. Multi-format Video Deinterlacer
26. Half-band Nyquist Decimation Filter
27. Motion-adaptive Video Deinterlacer
28. Complex Digital Down Converter
29. IIR Filter Second-Order-Section
30. Generic 8-way set-associative Read Cache
31. 32-bit Floating-point Adder
32. 16-bit Arctan Function
33. 32-bit Fixed-point to Floating-point Converter
34. Pipeline Register with generic width
35. 16-bit Sine Function
36. 32-bit Floating-point to Fixed-point Converter
37. Generic Single-line Read Cache
38. Generic Direct-mapped Read Cache
39. 16-bit Cosine Function
40. RF Power Amplifier Precorrection System
41. Binary-FSK Demodulator
42. Multi-ported Memory Controller
43. 18-bit Sincos Function
44. Video Frame Buffer / Genlock
45. Variable-Tap Video Scaling Engine
46. Precision Tone Decoder
47. High-Speed LVDS (SERDES) Transceiver
48. Spartan-6 Reference Design
49. BT.656 Decoder with Colour-Space Converter
50. HD Video Format Converter
 

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FIFOs, Datapath and Pipeline Elements Peripheral and Communications Interfaces Caches and Memory Management Fixed-point Mathematics IEEE Floating-point Mathematics Digital Signal Processing Digital Modulation Digital Video Processing
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