CALL US: +34 667 249 415    ZIPcores - Caches and Memory Management - Multi-ported Memory Controller Multi-ported Memory Controller   General Description Multi-ported Memory Controller/Arbiter permits a single memory component to be shared between multiple devices. Features a configurable number of read/write ports and a choice of different arbitration schemes. Optimized to reduce page-breaks in SDRAM, DDR and DDR2-based memory architectures. Key Design Features - Configurable no. of read/write ports - Single memory interface port - Configurable data width - Configurable address width - Configurable read/write burst size - Fully pipelined architecture - Continuous operation between port swaps - Choice of arbitration schemes - Fixed, Round-robin and page-break optimized - Suitable for all synchronous memory types   Including SDRAM, DDR, DDR2 Applications - Processor architectures - Synchronous memory designs - Any application where the memory bandwidth   must be shared efficiently between devices View full product datasheet: Details   SKU SKU44 Price: $1500.00 Options   Quantity 1 (this product is downloadable)   Also available in this category Generic 8-way set-associative Read Cache Generic Single-line Read Cache Generic Direct-mapped Read Cache Multi-ported Memory Controller

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