IP core deliverables
1. IP Core as synthesizable RTL source code for FPGA and ASIC
Our IP Cores are provided as clearly readable VHDL source code that is compatible with all well known synthesis tools including:
- Xilinx® Vivado & ISE
- Altera® Quartus
- Lattice® Diamond
- Microsemi® Libero
- Synopsys® Design Compiler
- Synplify Pro® FPGA
(Note that our language of choice is VHDL but we can also provide Verilog versions for an additional translation fee).
2. Test-bench for hardware simulation
Every IP Core is supplied with its own VHDL test-bench which instantiates the Core in an example configuration. Each test-bench is self-contained and generates input and output test vectors as a text file. All our IP Cores have been simulated and proven using Modelsim, the popular hardware simulator from Mentor Graphics®.
3. Comprehensive PDF datasheet
All our cores are backed up with a fully comprehensive datasheet. The datasheet includes everything needed to take full advantage of the IP.
4. Full one-year warranty
All our cores are guaranteed for one year. If you reasonably show that any aspect of our IP does not meet the functionality set out in the datasheet, then we will gladly modify the design free of charge or issue a full refund.
5. Free upgrades
You are entitled to free IP Core upgrades for one year after purchase (if applicable). Please keep in touch with us to ensure that you have the very latest source code.
6. Personal one-to-one email support
When you purchase our IP, you will be assigned a personal Design Engineer who will give you personal technical support via email for up to one year.
7. Single-site IP licensing agreement
You only need to pay once for the IP license. After that you can use the IP as many times as you wish in your own designs. You must, however, keep the source code confidential. With every core sold, we include the Zipcores IP License Agreement which outlines the legal aspects relating to the use of our IP. Please take time to read the agreement thoroughly before making a purchase.