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 IEEE Floating-point Mathematics
Zipcores - IEEE Floating-point Mathematics

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IEEE Floating-point Mathematics

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32-bit Floating-point Multiplier
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32-bit Floating-point Multiplier

High-speed fully pipelined 32-bit floating-point multiplier based on the IEEE 754 standard. Results have a latency of only 4 clock cycles. Ideal for floating-point pipelines, arithmetic units and processors.

Our price: $1500.00
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32-bit Floating-point Square-root
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32-bit Floating-point Square-root

High-speed fully pipelined 32-bit floating-point square-root function based on the IEEE 754 standard. Features a generic latency from 2 to 24 clock cycles. Ideal for floating-point pipelines, arithmetic units and processors.

Our price: $1500.00
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32-bit Floating-point Divider
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32-bit Floating-point Divider

High-speed fully pipelined 32-bit floating-point divider based on the IEEE 754 standard. Features a generic latency from 2 to 49 clock cycles. Ideal for floating-point pipelines, arithmetic units and processors.

Our price: $1500.00
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32-bit Floating-point Adder
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32-bit Floating-point Adder

High-speed fully pipelined 32-bit floating-point adder/subtracter based on the IEEE 754 standard. Results have a latency of 5 clock cycles. Ideal for floating-point pipelines, arithmetic units and processors.


Our price: $1500.00
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32-bit Floating-point to Fixed-point Converter
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32-bit Floating-point to Fixed-point Converter

Converts 32-bit floating-point numbers to fixed-point representation. The fixed-point output has a configurable word and fraction width. Floating-point inputs are based on the IEEE 754 standard. The design features a high-speed, fully pipelined architecture with a 2 clock-cycle latency.

Our price: $1500.00
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32-bit Fixed-point to Floating-point Converter
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32-bit Fixed-point to Floating-point Converter

Converts fixed-point numbers to 32-bit floating-point representation. The fixed-point input has a configurable word and fraction width. Floating-point outputs are based on the IEEE 754 standard. The design features a high-speed, fully pipelined architecture with a 2 clock-cycle latency.

Our price: $1500.00
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FIFOs, Datapath and Pipeline Elements Peripheral and Communications Interfaces Caches and Memory Management Fixed-point Mathematics IEEE Floating-point Mathematics Digital Signal Processing Digital Modulation Digital Video Processing
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