Generic Single-line Read Cache

General Description

Single-line read cache with configurable address width, word size and line size. The cache has a fully pipelined architecture with FIFO buffering on all ports and buffering to hide the latency of a cache miss. Ideal for small, level-1 processor caches.

Key Design Features

- One cache line
- Fully pipelined non-stalling architecture
- Cache flush functionality
- Configurable address width
- Configurable word size and line size
- Buffering to hide the memory latency
- Buffering on all input and output interfaces
- Cache performance metrics
- Simple valid/ready pipeline protocol
- 6 cycle cache hit latency

Applications

- Level-1 processor read caches
- Processor instruction caches
- General purpose read-data buffering

View full product datasheet:

Details


SKU	SKU6
Price:	$500.00

Options

Quantity

1 (this product is downloadable)

Generic Single-line Read Cache

Also available in this category