Generic Direct-mapped Read Cache

General Description Direct-mapped read cache with configurable address width, word size, line size and number of cache lines. The cache has a fully pipelined architecture with FIFO buffering on all ports and buffering to hide the latency of a cache miss. Ideal for level-2/3 processor caches or pixel caches. Key Design Features - Direct-mapped organization - Fully pipelined non-stalling architecture - Cache flush functionality - Register or RAM-based storage - Configurable address width - Configurable word size and line size - Configurable number of cache lines - Buffering to hide the memory latency - Buffering on all input and output interfaces - Cache performance metrics - Simple valid/ready pipeline protocol - 8 cycle cache hit latency Applications - Level-2 or level-3 processor read caches - General purpose read caches - Processor instruction caches - Pixel caches View full product datasheet: Details   SKU SKU7 Price: $1000.00 Options   Quantity 1 (this product is downloadable)