Generic 8-way set-associative Read Cache

General Description 8-way set-associative read cache with configurable address width, word size, line size and number of cache lines. The cache has a fully pipelined architecture with FIFO buffering on all ports and buffering to hide the latency of a cache miss. Offers the ultimate flexibility and performance in cache architectures. Ideal for large level-2/3 processor caches or pixel caches. Key Design Features - 8-way associativity - Fully pipelined non-stalling architecture - Cache flush functionality - Register or RAM-based storage - Configurable address width - Configurable word size and line size - Configurable number of cache lines - Buffering to hide the memory latency - Buffering on all input and output interfaces - Cache performance metrics - Simple valid/ready pipeline protocol - 8 cycle cache hit latency Applications - Level-2 or Level-3 processor read caches - Processor instruction caches - Pixel caches View full product datasheet: Details   SKU SKU8 Price: $1500.00 Options   Quantity 1 (this product is downloadable)