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IEEE Floating-point Mathematics
ZIPcores
-
IEEE Floating-point Mathematics
- Fixed-point to 32-bit Floating-point Converter
Printable version
Fixed-point to 32-bit Floating-point Converter
General Description
Converts fixed-point numbers to 32-bit floating-point representation. The fixed-point input has a configurable word and fraction width. Floating-point outputs are based on the IEEE 754 standard. The design features a high-speed, fully pipelined architecture with a 2 clock-cycle latency.
Key Design Features
- Signed fixed-point or integer input
- 32-bit floating-point output
- Configurable word width (up to 32-bits)
- Configurable fraction width (up to 23-bits)
- IEEE 754 compliant
- High-speed fully pipelined architecture
- Only 2 clock-cycles of latency
- FPGA clock rates of 300MHz+
- Low area footprint
Applications
- Floating-point pipelines and arithmetic units
- Floating-point processors
- Interfacing between float/fixed number systems
View full product datasheet:
Details
SKU
SKU15
Price:
$1000.00
Options
Quantity
1
(this product is downloadable)
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