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ZIPcores - FIFOs, Datapath and Pipeline Elements
FIFOs, Datapath and Pipeline Elements
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Pipeline Register with generic width
Self-flushing register element with a configurable data width. Data flows in and out of the register in accordance with a simple valid/ready pipeline interface protocol. The component is used as a fundamental building block in pipelined architectures.
Our price: $150.00
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Synchronous FIFO with generic width and depth
General purpose synchronous FIFO with configurable depth and data width. The component uses a simple valid/ready pipeline interface protocol and features full/empty flags and a FIFO fullness counter. The FIFO can be configured to use register or RAM-based storage.
Our price: $250.00
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Asynchronous FIFO with generic width
Asynchronous FIFO with configurable data width and a fixed depth of 16. The component uses Gray-coded read/write pointers for highest reliability when synchronizing between different clock domains. It uses a simple valid/ready pipeline interface protocol and features FIFO full and empty flags.
Our price: $500.00
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