Datapath and Pipeline

IP Cores for high-speed pipelined operations and data streaming
AXI4-Stream Protocol Interface
This service is a design-specific modification to any of our existing IP Cores to support the AMBA® 4 AXI4-Stream Protocol. The AXI4-Stream protocol is an open specification originated by ARM and is popular among many FPGA and ASIC vendors.
Asynchronous FIFO
Asynchronous FIFO optimized for very high-speed operation. Features a configurable data width and depth. The component uses Gray-coded read/write pointers for highest reliability when synchronizing between different clock domains. Ideal for asynchronous interfaces where speed it critical.
Synchronous FIFO
General purpose synchronous FIFO with configurable depth and data width. The component follows a simple valid-ready pipeline interface protocol and features full/empty flags and a FIFO fullness counter. The FIFO can be configured to use register or RAM-based storage.
Pipeline Register
Self-flushing register element with a configurable data width. Data flows in and out of the register in accordance with a simple valid-ready pipeline interface protocol. The component is used as a fundamental building block in pipelined architectures.