Customer Case Study 1

"Would it be possible to give me a size/speed estimate for the core set to unsigned,
with a 22-bit numerator and 13-bit divisor, targeted for an Altera Stratix-II
in the -4 speed grade (EP2S60-C4)? Thank you"

- Customer based in Richardson, TEXAS

A very common request from many of our customers is to give them area/speed estimates for a particular IP Core. In this example, our customer had a requirement for a large pipelined divider targeting an Altera® Stratix II device. In addition, the core was also required to time at 167MHz - quite a tight specification for such a large divider in the given technology. After initial synthesis trials using Altera® Quartus II, and various emails back and forth, the end result was a series of modifications to the original divider core.

Generic options were added to the divider to permit 245MHz operation with full pipelining for the chosen Stratix II device - or a design with half the number of pipeline stages clocking at 155 MHz. Ultimately, the customer chose the fully pipelined version. In addition, we also offered help with the testing and integration of the IP Core.

Conclusion

This small case study demonstrates the very common request to provide speed/area estimates for a particular IP core in a given device technology. At ZIPcores, we are happy to provide trial synthesis results as and when required and, as this example shows, we are also happy to modify an existing core and adapt it to fit the customer's requirements. What's more, most modifications and improvements find their way into future revisions of ZIPcores products.