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Multi-ported Memory Controller
Multi-ported Memory Controller/Arbiter permits a single memory component to be shared between multiple devices. Features a configurable number of read/write ports and a choice of different arbitration schemes. Optimized to reduce page-breaks in SDRAM, DDR and DDR2-based memory architectures.
Our price: $1500.00
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Generic 8-way set-associative Read Cache
8-way set-associative read cache with configurable address width, word size, line size and number of cache lines. The cache has a fully pipelined architecture with FIFO buffering on all ports and buffering to hide the latency of a cache miss. Offers the ultimate flexibility and performance.
Our price: $1500.00
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Generic Direct-mapped Read Cache
Direct-mapped read cache with configurable address width, word size, line size and number of cache lines. The cache has a fully pipelined architecture with FIFO buffering on all ports and buffering to hide the latency of a cache miss. Ideal for level-2/3 processor caches or pixel caches.
Our price: $1000.00
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Generic Single-line Read Cache
Single-line read cache with configurable address width, word size and line size. The cache has a fully pipelined architecture with FIFO buffering on all ports and buffering to hide the latency of a cache miss. Ideal for small, level-1 processor caches.
Our price: $500.00
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