Asynchronous FIFO with generic width

General Description Asynchronous FIFO with configurable data width and a fixed depth of 16. The component uses Gray-coded read/write pointers for highest reliability when synchronizing between different clock domains. It uses a simple valid/ready pipeline interface protocol and features FIFO full and empty flags. Key Design Features - Dual-clock architecture - Configurable data width - Gray-coded read/write pointers - Full/Empty flags - Simple valid/ready pipeline interface protocol - Output register option for improved timing Applications - Synchronizing between clock domains - Registering the datapath on and off chip - General purpose buffering and rate adaptation View full product datasheet: Details   SKU SKU5 Price: $500.00 Options   Quantity 1 (this product is downloadable)