Asynchronous FIFO with generic width

General Description Asynchronous FIFO optimized for very high-speed operation. Features a configurable data width and depth. The component uses Gray-coded read/write pointers for highest reliability when synchronizing between different clock domains. Ideal for asynchronous interfaces where speed it critical. Key Design Features - Dual-clock architecture - Configurable data width - Configurable depth of 8 or 16 entries - Gray-coded read/write pointers - FIFO Full and Empty flags - Simple valid/ready pipeline interface protocol - Output register option for improved timing - 500 MHz operation on standard FPGA platforms Applications - Synchronizing between clock domains - Registering the datapath into and off chip - General purpose buffering - Adapting to different data rates View full product datasheet: Details   SKU SKU5 Price: $750.00 Options   Quantity 1 (this product is downloadable)