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IEEE Floating-point Mathematics
ZIPcores
-
IEEE Floating-point Mathematics
- 32-bit Floating-point Multiplier
Printable version
32-bit Floating-point Multiplier
General Description
High-speed fully pipelined 32-bit floating-point multiplier based on the IEEE 754 standard. Results have a latency of only 4 clock cycles. Ideal for floating-point pipelines, arithmetic units and processors.
Key Design Features
- 32-bit floating-point arithmetic
- IEEE 754 compliant
- High-speed fully pipelined architecture
- Only 4 clock-cycles of latency
- FPGA clock rates of 300MHz+
- Low area footprint
Applications
- Floating-point pipelines and arithmetic units
- Floating-point processors
View full product datasheet:
Details
SKU
SKU12
Price:
$1500.00
Options
Quantity
1
(this product is downloadable)
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