CALL US: +34 667 249 415    ZIPcores - IEEE Floating-point Mathematics - 32-bit Floating-point Adder 32-bit Floating-point Adder   General Description High-speed fully pipelined 32-bit floating-point adder/subtracter based on the IEEE 754 standard. Results have a latency of 5 clock cycles. Ideal for floating-point pipelines, arithmetic units and processors. Key Design Features - 32-bit floating-point arithmetic - IEEE 754 compliant - High-speed fully pipelined architecture - Only 5 clock-cycles of latency - FPGA clock rates of 300MHz+ - Low area footprint Applications - Floating-point pipelines and arithmetic units - Floating-point processors View full product datasheet: Details   SKU SKU13 Price: $1500.00 Options   Quantity 1 (this product is downloadable)   Also available in this category Fixed-point to 32-bit Floating-point Converter 32-bit Floating-point Adder 32-bit Floating-point Multiplier 32-bit Floating-point to Fixed-point Converter

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