ZIPcores IP Cores for FPGA, CPLD and ASIC
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ZIPcores IP Cores for FPGA, CPLD and ASIC
ZIPcores IP Cores for FPGA, CPLD and ASIC   ZIPcores IP Cores for FPGA, CPLD and ASIC
ZIPcores IP Cores for FPGA, CPLD and ASIC
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ZIPcores IP Cores for FPGA, CPLD and ASIC
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 IEEE Floating-point Mathematics
Zipcores - IEEE Floating-point Mathematics - 32-bit Floating-point Adder

32-bit Floating-point Adder

32-bit Floating-point Adder 

General Description

High-speed fully pipelined 32-bit floating-point adder/subtracter based on the IEEE 754 standard. Results have a latency of 5 clock cycles. Ideal for floating-point pipelines, arithmetic units and processors.

Key Design Features

- 32-bit floating-point arithmetic
- IEEE 754 compliant
- High-speed fully pipelined architecture
- Only 5 clock-cycles of latency
- FPGA clock rates of 300MHz+
- Low area footprint

IEEE Floating-point Adder Subtractor

Applications

- Floating-point pipelines and arithmetic units
- Floating-point processors

View full product datasheet: IEEE Floating-point Adder Subtractor

Details
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SKU SKU13
Price: $1500.00

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