ZIPcores IP Cores for FPGA, CPLD and ASIC
Home  |  Sitemap  |  Login  |  Register  |  View Cart Shopping trolly empty
ZIPcores IP Cores for FPGA, CPLD and ASIC
ZIPcores IP Cores for FPGA, CPLD and ASIC   ZIPcores IP Cores for FPGA, CPLD and ASIC
ZIPcores IP Cores for FPGA, CPLD and ASIC
Search: Go button Advanced search
ZIPcores IP Cores for FPGA, CPLD and ASIC
10 pixel spacer
ZIPcores home What we do What we provide How it works Testimonials List of cores Contact and Support Request a core
10 pixel spacer
ZIPcores welcome bar top section

ZIPcores design and sell Intellectual Property (IP Cores) for implementation on Semiconductor Devices.
We offer a wide range of cores for a variety of application areas from basic building blocks to more complex systems. Our IP Cores are written in VHDL and are synthesizable across multiple technologies - whether it be FPGA, CPLD or ASIC.
Click on a core category to expand the list of available cores.

 ZIPcores welcome bar bottom section
10 pixel spacer
FIFOs, Datapath and Pipeline Elements Peripheral and Communications Interfaces Caches and Memory Management Fixed-point Mathematics IEEE Floating-point Mathematics Digital Signal Processing Digital Modulation Digital Video Processing
10 pixel spacer

News

Mar 8, 2010

We have released a new high speed generic Video Frame Buffer suitable for all common 16, 24 and 32-bit digital video formats.

With FPGA clock rates in excess of 350MHz, there's no need to worry about video bandwidth problems any more!

Video Frame Buffer

The VFB offers a generic 32-bit memory interface with programmable burst transfers optimized for all synchronous memory types - whether it be normal SDRAM or the latest DDR3 technology.

Spartan 6 comment

Also, why not request our new Xilinx® Spartan 6 VFB reference design. The design interfaces directly to the embedded Spartan 6 Memory Controller Block (MCB).

Designing memory interfaces has never been easier!

Click here to learn more!

ZIPcores RSS feed

Bookmark and Share

Previous news
8 pixel spacer
Your e-mail:
Subscribe Go menu button
200 pixel spacer

Featured products


Video Frame Buffer / Genlock
See details 		Video Frame Buffer / Genlock

Video Frame buffer permits an asynchronous video source to be buffered in an external memory. Features a generic 32-bit memory interface suitable for all memory types including SDRAM, DDR2, DDR3 etc. Ideal for adapting to different pixel rates and frame rates. Scalable architecture.
Our price: $4725.00
Buy Now
Add to wish list



Variable-Tap Video Scaling Engine
See details 		Variable-Tap Video Scaling Engine

Video up/down scaler with a variable number of filter taps. Offers higher quality results when downscaling by factors of 2 or more - e.g. the generation of 'thumbnail' images. Proprietary algorithm offers a choice filter sizes from 2x2 to 8x8 taps. Easy to use. No coefficient programming required.
Our price: $5775.00
Buy Now
Add to wish list



 

Click here to view our refund policy and terms and conditions of sale

ZIPcores is a leading provider of IP Cores written in VHDL for ASIC, FPGA, and CPLD platforms. We offer a bespoke design service and a range of ready-to-use IP Cores via our e-commerce site. What's more, our IP Cores are compatible with all major vendors including Xilinx® Altera® and Actel® FPGAs. Click on a customer case study to see one of our recent projects:


ZIPcores case study 1     ZIPcores case study 2     ZIPcores case study 3


ZIPcores case study 4     ZIPcores case study 5


McAfee Secure sites help keep you safe from identity theft, credit card fraud, spyware, spam, viruses and online scams

 

Bestsellers

1. 16-bit Direct Digital Synthesizer / Periodic waveform generator
2. Digital Video Scaling Engine
3. I2C Slave Serial Interface Controller
4. I2C Master Serial Interface Controller
5. Bilinear Video Scaling Engine
6. Asynchronous FIFO with generic width
7. Synchronous FIFO with generic width and depth
8. Pipelined Divider with generic width
9. SPI Master Serial Interface Controller
10. SPI Slave Serial Interface Controller
11. High-speed symmetrical FIR Filter with an Even number of taps
12. High-speed symmetrical FIR Filter with an Odd number of taps
13. Text Overlay Module
14. Digital Video Overlay Module
15. Generic Ultra-speed FIR Filter
16. IIR Filter Second-Order-Section
17. 16-bit Arctan Function
18. Generic 8-way set-associative Read Cache
19. Fixed-point to 32-bit Floating-point Converter
20. Pipeline Register with generic width
21. 32-bit Floating-point Adder
22. UART Serial Interface Controller
23. 32-bit Floating-point Multiplier
24. 16-bit Sine Function
25. 32-bit Floating-point to Fixed-point Converter
26. Pipelined Square Root with generic width
27. Generic Single-line Read Cache
28. Pipelined Multiplier with generic width and depth
29. Generic Direct-mapped Read Cache
30. 16-bit Cosine Function
31. 4-Quadrant Arctan Function
32. RF Power Amplifier Precorrection System
33. Multi-ported Memory Controller
34. 18-bit Sincos Function
35. 2D Graphics Overlay Module
36. Binary-FSK Demodulator
37. Precision Tone Decoder
38. Video Timing Generator
39. Variable-Tap Video Scaling Engine
40. Video Frame Buffer / Genlock
41. Video Test Pattern Generator

200 pixel spacer
ZIPcores Development Centre ZIPcores IP Core compatibility Xilinx Lattice Semiconductor Quicklogic
ZIPcores Development Centre ZIPcores IP compatibility Altera Actel TSMC
10 pixel spacer
ZIPcores footer bar section 1 Copyright © 2008-2010 ZIPcores ZIPcores footer bar section 2
PayPal logo Credit card logos