ZIPcores IP Cores for FPGA, CPLD and ASIC ZIPcores IP Cores for FPGA, CPLD and ASIC
ZIPcores IP Cores for FPGA, CPLD and ASIC   ZIPcores IP Cores for FPGA, CPLD and ASIC
ZIPcores IP Cores for FPGA, CPLD and ASIC
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ZIPcores IP Cores for FPGA, CPLD and ASIC
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ZIPcores design and sell Intellectual Property (IP Cores) for implementation on Semiconductor Devices.
We offer a wide range of cores for a variety of application areas from basic building blocks to more complex systems. Our IP Cores are written in VHDL and are synthesizable across multiple technologies - whether it be FPGA, CPLD or ASIC.
Click on a core category to expand the list of available cores.

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FIFOs, Datapath and Pipeline Elements Peripheral and Communications Interfaces Caches and Memory Management Fixed-point Mathematics IEEE Floating-point Mathematics Digital Signal Processing Digital Modulation Digital Video Processing
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News

May 24, 2010

Our Versatile Video Controller Core (VVC) is a high performance video processor with integrated dual frame buffer, high-quality video scaling and PiP support.

VVC core news 1

Implementing key video IP in one unique package, the VVC core is ideal for a wide range of multi-format displays including: PiP, dual-screen, scaled and blended video overlays.

VVC core news 2

What's more, the VVC core is easy to integrate into all FPGA technologies - clocking at 200MHz on even the most basic platforms.

Spartan 6

Also, why not request our new Xilinx® Spartan 6 VVC reference design and give a new lease of life to your video products!

Click here to learn more!

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Featured products


Digital Video Scaling Engine
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Digital Video Scaling Engine

Digital Video up/down scaler accepts RGB video and permits independent horizontal and vertical scaling of the input to generate any desired resolution or aspect ratio. Uses a series of FIR polyphase filter banks to generate a studio-quality interpolated output image. Ideal for Digital TV.

Our price: $4500.00
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Video Frame Buffer / Genlock
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Video Frame Buffer / Genlock

Video Frame buffer permits an asynchronous video source to be buffered in an external memory. Features a generic 32-bit memory interface suitable for all memory types including SDRAM, DDR2, DDR3 etc. Ideal for adapting to different pixel rates and frame rates. Scalable architecture.

Our price: $3000.00
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Spartan-6 Reference Design
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Spartan-6 Reference Design

We can provide a low-cost Xilinx® Spartan-6 design platform for most of our Digital Video IP. If you would like to trial any of our designs, then please contact us with your specific requirements.



Price on request
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Click here to view our refund policy and terms and conditions of sale

ZIPcores is a leading provider of IP Cores written in VHDL for ASIC, FPGA, and CPLD platforms. We offer a bespoke design service and a range of ready-to-use IP Cores via our e-commerce site. What's more, our IP Cores are compatible with all major vendors including Xilinx® Altera® and Actel® FPGAs. Click on a customer case study to see one of our recent projects:


ZIPcores case study 1     ZIPcores case study 2     ZIPcores case study 3


ZIPcores case study 4     ZIPcores case study 5

 

Bestsellers

1. 16-bit Direct Digital Synthesizer / Periodic waveform generator
2. Digital Video Scaling Engine
3. I2C Slave Serial Interface Controller
4. I2C Master Serial Interface Controller
5. Bilinear Video Scaling Engine
6. Asynchronous FIFO with generic width
7. SPI Slave Serial Interface Controller
8. Synchronous FIFO with generic width and depth
9. SPI Master Serial Interface Controller
10. Pipelined Divider with generic width
11. High-speed symmetrical FIR Filter with an Even number of taps
12. High-speed symmetrical FIR Filter with an Odd number of taps
13. Text Overlay Module
14. Digital Video Overlay Module
15. Generic Ultra-speed FIR Filter
16. IIR Filter Second-Order-Section
17. Generic 8-way set-associative Read Cache
18. 16-bit Arctan Function
19. Fixed-point to 32-bit Floating-point Converter
20. 32-bit Floating-point Adder
21. Pipeline Register with generic width
22. UART Serial Interface Controller
23. 32-bit Floating-point Multiplier
24. 16-bit Sine Function
25. 32-bit Floating-point to Fixed-point Converter
26. Pipelined Square Root with generic width
27. Generic Single-line Read Cache
28. Pipelined Multiplier with generic width and depth
29. Generic Direct-mapped Read Cache
30. 16-bit Cosine Function
31. 4-Quadrant Arctan Function
32. RF Power Amplifier Precorrection System
33. Multi-ported Memory Controller
34. 2D Graphics Overlay Module
35. 18-bit Sincos Function
36. Binary-FSK Demodulator
37. Video Frame Buffer / Genlock
38. Variable-Tap Video Scaling Engine
39. Video Timing Generator
40. Precision Tone Decoder
41. Video Test Pattern Generator
42. Versatile Video Controller
43. Spartan-6 Reference Design
44. Motion-Adaptive Video De-interlacer

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