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Video Frame Buffer / Genlock
Video Frame buffer permits an asynchronous video source to be buffered in an external memory. Features a generic 32-bit memory interface suitable for all memory types including SDRAM, DDR2, DDR3 etc. Ideal for adapting to different pixel rates and frame rates. Scalable architecture.
Our price: $4725.00
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Variable-Tap Video Scaling Engine
Video up/down scaler with a variable number of filter taps. Offers higher quality results when downscaling by factors of 2 or more - e.g. the generation of 'thumbnail' images. Proprietary algorithm offers a choice filter sizes from 2x2 to 8x8 taps. Easy to use. No coefficient programming required.
Our price: $5775.00
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ZIPcores is a leading provider of IP Cores written in VHDL for ASIC, FPGA, and
CPLD platforms. We offer a bespoke design service and a range of ready-to-use
IP Cores via our e-commerce site. What's more, our IP Cores are compatible with
all major vendors including Xilinx® Altera® and Actel® FPGAs. Click
on a customer case study to see one of our recent projects:
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